The present invention generally relates to generating clock pulses and in particular to generating a stable high-speed clock pulse train by employing a negative resistance oscillator operating at an overtone frequency of a resonator.
Applications such as communications, video processing, data acquisition and recovery, and high-bandwidth test systems require stable high frequency clocks to meet specific performance demands and provide periodic and accurately spaced signals. Most clocks include an electronic device, e.g., an oscillator, to generate an accurate oscillating signal. This signal oscillation is based on a periodic event that, under the control of a resonator, repeats at a natural and substantially constant rate, i.e., a fundamental or resonance frequency.
Stability is an inherent property that determines how well an oscillator can produce the same frequency over a given time interval. The more stable the oscillator, the more accurately the fundamental frequency is produced, and the less variations there will be in signal characteristics. Additionally, quality factor, or Q, is another inherent oscillator quality that influences stability. In general, oscillators having a high quality factor tend to be more stable, experience fewer signal characteristic variations, and operate in a range close to its natural resonance frequency.
Conventional oscillators, often utilize a crystal unit to generate an oscillating signal, e.g., a clock pulse train, and ideally maintain a constant spacing between clock transitions. However, in some applications short-term leading or lagging variations of the significant instants of the oscillating signal from its ideal positions in time occur, such that the transition spacing varies. This uncertainty, called clock jitter, directly affects timing margins and hence limits system performance. Clock jitter can be caused by temperature and voltage variations over time; changing environmental conditions; manufacturing variations; and so forth. Jitter may be characterized by the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. Oscillators using crystal units are often plagued by jitter effects.
For instance, as a drive current through a crystal unit increases, the crystal's amplitude of vibration also increases, and jitter effects due to the nonlinearities of quartz can become more pronounced. In general, the frequency change with drive level of the oscillator is proportional to the square of the drive current. Thus, drive current fluctuations, such as those resulting from drive or voltage source variations, can induce frequency fluctuations in the crystal unit. In addition, resistive properties of crystal units can increase non-linearly with the drive current. Therefore variations in the drive current can inject undesirable instabilities into an oscillator, and thus, be an additional source of jitter.
Some conventional oscillators employ a Colpitts configuration, in which a quartz crystal is operated at its fundamental frequency in the parallel mode, and is connected in the positive feedback loop of the oscillator sustaining circuit/amplifier. However, most applications require operating frequencies substantially higher than the natural resonance or fundamental frequency of a crystal. Unfortunately, high frequency fundamental mode crystals, for example, above 20 MHz, can be expensive and be difficult to manufacture. Also, high frequency fundamental mode crystals tend to have less stability and greater aging rates.
As such, various techniques can be used to multiply the fundamental frequency to produce the actual output frequency of the oscillator. For example, a device such as a phase-locked loop (PLL) can be used to multiply the fundamental frequency to a desired operating frequency. Although achieving frequencies higher than the fundamental frequency, PLLs require additional circuitry which increases the number of possible sources of jitter. Indeed, jitter introduced by a PLL is generally proportional to the square of the number of stages in the PLL. Moreover, the effects of jitter can be magnified as operating frequencies increase.
Additionally, some applications, such as data transmission system designs, e.g., SONET, Gigabit Ethernet, and Fiber Channel, employ circuits operating at high frequencies, and place strict demands on the allowable jitter for the system's reference clock oscillator. Excessive clock jitter can degrade the system performance due to uncertainty in the position of the signal's rising edge which in turn causes an unacceptable bit error rate.